CVE-2024-42279
- Source
- https://nvd.nist.gov/vuln/detail/CVE-2024-42279
- Import Source
- https://storage.googleapis.com/osv-test-cve-osv-conversion/osv-output/CVE-2024-42279.json
- JSON Data
- https://api.test.osv.dev/v1/vulns/CVE-2024-42279
- Downstream
- Related
- Published
- 2024-08-17T09:15:08Z
- Modified
- 2025-10-02T18:32:28Z
- Severity
-
- 5.5 (Medium) CVSS_V3 - CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H CVSS Calculator
- Summary
- [none]
- Details
-
In the Linux kernel, the following vulnerability has been resolved:
spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
- References